BlueJay Retimer Chiplet with Credo's Advanced Mixed-Signal DSP Technology Enables High-Performance, Low-Power Solutions for Advanced Switching, Compute, AI, and Machine Learning Devices
SAN JOSE, Calif., December 01, 2021--(BUSINESS WIRE)--Credo, a global leader in high performance, low-power connectivity solutions for 100G, 200G, 400G, and 800G port-enabled networks, today announced the production availability of the new 3.2Tbps BlueJay retimer chiplet. BlueJay provides robust system-level connectivity with 64 lanes of 56Gbps PAM4 LR DSP connectivity. The new device delivers low-power and system-reach performance for next-generation multi-chip-module (MCM) ASICs used in advanced switching, high-performance computing, artificial intelligence (AI), and machine learning applications.
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The new chiplet delivers low-power and system-reach performance for next-generation multi-chip-module (MCM) ASICs used in advanced switching, high-performance computing, artificial intelligence (AI), and machine learning applications. (Graphic: Business Wire)
BlueJay communicates with the MCM system-on-chip (SoC) core on the host side using an ultra-low-power Bunch of Wires (BoW) die-to-die interface. The wide-bus BoW interface is optimized for the TSMC CoWoS packaging technology designed for high-performance computing applications. On the line side, the chiplet has 64 lanes of low-power 56G PAM4 LR SerDes to deliver a robust, off-package interface for the MCM, which allows for easy integration in various system-level configurations.
"Integrating chiplets allows our customers to accelerate ASIC designs with increased performance to support advanced switching, storage, high-performance computing, AI, machine learning, and service provider applications. These data intensive applications place a wide range of architectural demands on next-generation ASICs," said Michael Girvan Lampe, Vice President of Worldwide Sales at Credo.
"BlueJay is the second Credo 3.2Tbps retimer chiplet to enter production this year. All of Credo's silicon-proven chiplets, with 56G and 112G lane rates plus SerDes DSP IP, provide ASIC designers with diverse options to achieve their time-to-market and performance objectives," Lampe continued.
Credo's unique SerDes technology allows the BlueJay chiplet to be manufactured in TSMC's 28nm process and delivers on critical performance and low-power requirements, in contrast to competing solutions manufactured in costly advanced process technologies. Credo’s optimized device architecture enables the use of the power-efficient BoW interface, facilitating the offload of SerDes from the ASIC, and simplifying its integration on the MCM SoC.
Integrating chiplets into MCM designs accelerates ASIC innovation and the system deployment required to meet the increasing performance demands of network service providers and hyperscale data centers. By moving the on-die SerDes function off-chip, up to 30% of the ASIC die area can now be repurposed for features such as extra compute, increased switching performance, and deeper routing tables.
"Networking and data center architectures are transitioning their infrastructure from 400Gbps to 800Gbps and beyond, requiring higher-performance, lower-power ASICs that combine digital core and analog interface functionality," said Alan Weckel, Founder and Technology Analyst at 650 Group. "However, achieving performance in a monolithic ASIC component is challenging since analog and digital process nodes advance at different rates. Multi-chip modules using Credo’s retimer chiplets decouple the analog interface from the digital core ASIC, reducing costs, lowering risk, and enabling the accelerated transition cycle."
For more information about BlueJay and other industry-leading Credo connectivity solutions, visit https://www.credosemi.com/serdes-ip-and-chiplets.
Credo is a leading provider of high-performance serial connectivity solutions for the hyperscale datacenter, 5G carrier, enterprise networking, artificial intelligence, and high-performance computing markets. Credo's solutions deliver the bandwidth, scalability, and end-to-end signal integrity for next-generation platforms requiring 25G, 50G, and 100G signal lane-rate connectivity for 100G, 200G, 400G, and 800G port enabled networks.
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