The global electronic design automation tools (EDA) market (hereafter referred to as the market studied) was valued at USD 11. 57 billion in 2020, and it is expected to reach USD 21. 36 billion by 2026, registering a CAGR of 10.
New York, Jan. 07, 2022 (GLOBE NEWSWIRE) -- Reportlinker.com announces the release of the report "Global Electronic Design Automation Tools (EDA) Market - Growth, Trends, COVID-19 Impact, and Forecasts (2021 - 2026)" - https://www.reportlinker.com/p06195689/?utm_source=GNW
41% during the period of 2021-2026 (henceforth referred to as the forecast period).
According to World Semiconductor Trade Statistics (WSTS), the semiconductor industry is expected to grow by 10.9% in 2021, which is a significant growth compared to the previous year’s growth, approximately amounting to USD 488 billion. Owing to this, various semiconductor vendors are expected to increase their R&D budgets. For instance, in April 2021, Taiwan Semiconductor Manufacturing Corporation ( TSMC) announced to spend USD 100 billion over the next three years to expand its chip fabrication capacity and R&D.
The upcoming trend of EDA toolset with machine learning capabilities along with the latest technology such as cloud, AI also contributes to the growth of the market studied. Significant investments that were made during the last couple of years which are aimed at empowering designers for the reduction of the number of errors, thereby saving significant time, are expected to produce results in the future.
For instance, in June 2020, Samsung Electronics Co. Ltd announced the launch of the Samsung Advanced Foundry Ecosystem (SAFE) Cloud Design Platform (CDP) for fabless customers, in collaboration with Rescale, a leader in high-performance computing (HPC) applications in the cloud. SAFE CDP supports a very secure design condition that has been verified with cloud companies. In addition, customers can utilize various Electronic Design Automation (EDA) tools offered by multiple vendors such as Ansys, Cadence, Mentor (a Siemens business), and Synopsys.
The factors driving the growth of the market studied include the rising demand for miniature electronic devices and the increasing adoption of SoC technology across various industries, such as automotive, IoT, and AI.
Moreover, AI is giving EDA a new dimension for addressing the increased complexity of silicon technologies, accelerating product timelines, and enabling engineering teams to scale. Further, the increasing demand for advanced electronic devices with complex designs, and the need to reduce the size while improving the performance of ICs, compels IC manufacturers to increase their R&D investments and adopt EDA tools. Therefore, the demand for EDA tools, compared to the other sectors, is expected to be high.
Key Market Trends
IC Physical Design and Verification Segment to Grow Significantly
IC physical design refers to the creation of geometric representations of ICs, using EDA tools. EDA is used to divide the chip into smaller blocks and then plan the specific space required for each block to ensure maximum performance. These blocks are then placed, using before and after clock synthesis.
The recent technological advancements have been helping several chipset manufacturers to make use of ASIC technology, mainly for 5G. The advent of structured ASIC, having elements of both ASICs and field-programmable gate arrays (FPGA), like architecture, has led to the cost of production becoming cheaper when compared to full-blown ASIC which requires the addition of a modifiable layer on top of the base ASIC layer.
In fact, owing to such advantages, several chipset manufacturers and telecom OEMs have been expanding their operations toward constructing 5G chipsets with ASIC technology. For instance, Intel developed Diamond Mesa in January 2020, which is the first next-generation structured ASIC for 5G network acceleration.
Recently, Samsung has also developed 5G mmWave chipsets, which comprise digital/analog front-end (DAFE) ASICs. These are low in power consumption and compact in size, thus, proving to be beneficial for 5G chipsets.
Mediatek, one of the prominent vendors in the chipset market, claims that sales of the new 5G ASIC solutions, along with automotive chip solutions, will be responsible for 15% of its 2020 revenues, instead of the predicted earlier 10%. This is evident by the fact that the company launched ’Dimensity 800 Series’ chips for the premium yet mid-price range 5G smartphones in 2020.
North America is Expected to Hold a Significant Market Share
EDA tools are often used to design circuit boards, processors, and other types of complex electronics. The adoption of EDA tools in industries, such as consumer electronics, automotive, is set to increase demand for the market in North America. Also, growing developments in the semiconductor industry and circuit manufacturing industry have raised the market’s prominence in the region. Also, some of the significant vendors of EDA tools are headquartered in North America, such as Xilinx Inc., Ansys Inc., Keysight Technologies Inc., Cadence Design Systems Inc., and Synopsys Inc.
To cater to the demand for EDA tools in the region, some of the vendors in North America have been investing in upgrading their offerings and expanding their presence. For instance, in March 2020, Synopsys Inc. announced a discovery in electronic design technology with the introduction of DSO.ai (Design Space Optimization AI), the industry’s first autonomous AI application for chip design. The design space AI is part of a multiyear, company-wide initiative and strategic investment in AI-based design technology. The solution revolutionizes the process of searching for optimal solutions by enabling autonomous optimization of broad design spaces. Hence, such innovations are expected to support the market’s growth over the forecast period.
Some of the vendors have continued to see strong demand from their customers, who are looking forward to accelerating their digital transformation as engineering teams adapt to increasing competition and shrinking time to market windows. For this, in November 2020, EMA Design Automation expanded its operations in North America through the addition of the Trilogic EDA engineering sales and support team to bring the latest technologies and support to the EDA industry in North America.
In June 2021, Taiwan-based Semiconductor Manufacturing Co. Ltd (TSMC) started construction at a site in Arizona where it plans to spend USD 12 billion to build a computer chip factory, which will start volume production of chips using the company’s 5-nanometer production technology starting in 2024. The company also announced a USD 100 billion investment plan in April 2021 to increase capacity at its factories over the next three years.
The United States is a significant country in manufacturing, design, and research in the semiconductor industry. The region’s prominence drives the demand in exporting electronics equipment and growing end-user industries that are significant consumers of semiconductors, such as consumer electronics and the automotive industry. For instance, according to the SIA(Semiconductor Industry Association), the semiconductor industry employs nearly a quarter of a million workers in the United States. The US semiconductor company sales totaled USD 208 billion in 2020.
The EDA market is highly fragmented. New opportunities in the automotive, IoT, artificial intelligence, and virtual/augmented reality sectors have allowed semiconductor companies throughout all phases of the IC production cycle to prosper, with sizable revenue increases. This has occurred despite significant gains in chip performance but at relatively flat unit sales prices. Some of the key players in the industry include Synopsis, Keysight Technologies, ANSYS, Cadence Design Systems, etc. Some of the key developments in the EDA market are as follows:
June 2021 - Aldec Inc. launched HES-DVM Proto Cloud Edition (CE). It is available through Amazon Web Service (AWS); HES-DVM Proto CE can be used for FPGA-based prototyping of SoC / ASIC designs and focuses on automated design partitioning to greatly reduce bring-up time when up to four FPGAs are needed to accommodate a design.
May 2021 - Cadence Design Systems announced low-power IP for the PCI Express 5.0 specification that targets hyper-scale computing, networking, and storage applications that are made on TSMC N5 process technology. In addition, PCIe 5.0 technology consists of a PHY, companion controller, and Verification IP (VIP) targeted at SoC designs for very high bandwidth to suit the applications.
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